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72-mbit (2m x 36/4m x 18/1m x 72) pipelined s y nc sram cy7c1480v33 cy7c1482v33 cy7c1486v33 preliminary cypress semiconductor corporation ? 3901 north first street ? san jose , ca 95134 ? 408-943-2600 document #: 38-05283 rev. *c revised december 3, 2004 features ? supports bus operation up to 250 mhz ? available speed grades are 250, 200,167 mhz ? registered inputs and outputs for pipelined operation ? 3.3v core power supply ? 2.5v / 3.3v i/o operation ? fast clock-to-output times ? 3.0 ns (for 250-mhz device) ? 3.0 ns (for 200-mhz device) ? 3.4 ns (for 167-mhz device) ? provide high-performance 3-1-1-1 access rate ? user-selectable burst counter supporting intel ? pentium ? interleaved or linear burst sequences ? separate processor and controller address strobes ? synchronous self-timed writes ? asynchronous output enable ? single cycle chip deselect ? cy7c1480v33 and cy7c1482v33 offered in jedec-standard lead-free 100-pin tqfp, 165-ball fbga packages. cy7c1486v33 available in 209-ball bga packages ? ieee 1149.1 jtag-compatible boundary scan ? ?zz? sleep mode option functional description [1] the cy7c1480v33/cy7c1482v33/cy7c1486v33 sram integrates 2,097,152 x 36/4, 194,304 x 18,1,048,576 72 sram cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. all synchronous inputs are gated by registers controlled by a positive-edge-triggered clock input (clk). the synchronous inputs include all addresses, all data inputs, address-pipelining chip enable (ce 1 ), depth-expansion chip enables (ce 2 and ce 3 ), burst control inputs (adsc , adsp , and adv ), write enables (bw x , and bwe ), and global write (gw ). asynchronous inputs include the output enable (oe ) and the zz pin. addresses and chip enables are registered at rising edge of clock when either address strobe processor (adsp ) or address strobe controller (adsc ) are active. subsequent burst addresses can be internally generated as controlled by the advance pin (adv ). address, data inputs, and write co ntrols are registered on-chip to initiate a self-timed write cycl e.this part supports byte write operations (see pin descriptions and truth table for further details). write cycles can be one to two or four bytes wide as controlled by the byte write control inputs. gw when active low causes all bytes to be written. the cy7c1480v33/cy7c1482v33/cy7c1486v33 operates from a +3.3v core power supply while all outputs may operate with either a +2.5 or +3.3v supply. all inputs and outputs are jedec-standard jesd8-5-compatible. selection guide 250 mhz 200 mhz 167 mhz unit maximum access time 3.0 3.0 3.4 ns maximum operating current 500 500 450 ma maximum cmos standby current 120 120 120 ma shaded areas contain advance information. please contact your local cypress sales representative for availability of these parts. note: 1. for best-practices recommendations, please refer to the cypress application note system design guidelines on www.cypress.com.
cy7c1480v33 cy7c1482v33 cy7c1486v33 preliminary document #: 38-05283 rev. *c page 2 of 30 1 2 logic block diagram ? cy7c1480v33 (2m x 36) address register adv clk burst counter and logic clr q1 q0 adsp adsc mode bwe gw ce 1 ce 2 ce 3 oe enable register output registers sense amps output buffers e pipelined enable input registers a 0, a1, a bw b bw c bw d bw a memory array dqs dqp a dqp b dqp c dqp d sleep control zz a [1:0] 2 dq a , dqp a byte write register dq b , dqp b byte write register dq c , dqp c byte write register dq d , dqp d byte write register dq a , dqp a byte write driver dq b , dqp b byte write driver dq c , dqp c byte write driver dq d ,dqp d byte write driver a 0, a1, a address register adv clk burst counter and logic clr q1 q0 adsc bw b bw a ce 1 dq b, dqp b write register dq a, dqp a write register enable register oe sense amps memory array adsp 2 mode ce2 ce3 gw bwe pipelined enable dqs dqp a dqp b output registers input registers e dq a, dqp a write driver output buffers dq b, dqp b write driver a[1:0] zz sleep control logic block diagram ? cy7c1482v33 (4m x 18)
cy7c1480v33 cy7c1482v33 cy7c1486v33 preliminary document #: 38-05283 rev. *c page 3 of 30 bw d bw c bw b bw a bwe gw ce1 ce2 ce3 oe enable register pipelined enable address register adv clk binary counter clr q1 q0 adsp adsc mode a 0, a1,a a[1:0] bw f bw e bw h bw g dqs dqp a dqp b dqp c dqp d dqp e dqp f dqp g dqp h output registers memory array output buffers e dq a , dqp a write driver dq b , dqp b write driver dq c , dqp c write driver dq d , dqp d write driver input registers byte ?a? write driver dq e , dqp e write driver dq f , dqp f write driver dq g , dqp g write driver dq h , dqp h write driver sense amps sleep control zz dq a , dqp a write driver dq b , dqp b write driver dq c , dqp c write driver dq d , dqp d write driver dq e , dqp e write driver dq f , dqp f write driver dq f , dqp f write driver dq h , dqp h write driver logic block diagram ? cy7c1486v33 (1m x 72)
cy7c1480v33 cy7c1482v33 cy7c1486v33 preliminary document #: 38-05283 rev. *c page 4 of 30 pin configurations dqp b dq b dq b v ddq v ssq dq b dq b dq b dq b v ssq v ddq dq b dq b v ss nc v dd zz dq a dq a v ddq v ssq dq a dq a dq a dq a v ssq v ddq dq a dq a dqp a dqp c dq c dqc v ddq v ssq dq c dq c dq c dq c v ssq v ddq dq c dq c v dd nc v ss dq d dq d v ddq v ssq dq d dq d dq d dq d v ssq v ddq dq d dq d dqp d a a ce 1 ce 2 bw d bw c bw b bw a ce 3 v dd v ss clk gw bwe oe adsc adsp adv a a 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 cy7c1480v33 (2m x 36) nc a a a a a 1 a 0 a a v ss v dd a a a a a a a a a nc nc v ddq v ssq nc dqp a dq a dq a v ssq v ddq dq a dq a v ss nc v dd zz dq a dq a v ddq v ssq dq a dq a nc nc v ssq v ddq nc nc nc nc nc nc v ddq v ssq nc nc dq b dq b v ssq v ddq dq b dq b v dd nc v ss dq b dq b v ddq v ssq dq b dq b dqp b nc v ssq v ddq nc nc nc a a ce 1 ce 2 nc nc bw b bw a ce 3 v dd v ss clk gw bwe oe adsc adsp adv a a 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 mode cy7c1482v33 (4m x 18) nc 100-pin tqfp pinout a a a a a a 1 a 0 a a v ss v dd a a a a a a a a mode a
cy7c1480v33 cy7c1482v33 cy7c1486v33 preliminary document #: 38-05283 rev. *c page 5 of 30 pin configurations (continued) 165-ball fbga cy7c1480v33 (2m x 36) 234 567 1 a b c d e f g h j k l m n p r tdo nc / 288m nc dqp c dq c dqp d nc dq d ce 1 bw b ce 3 bw c bwe a ce2 dq c dq d dq d mode nc dq c dq c dq d dq d dq d a a v ddq bw d bw a clk gw v ss v ss v ss v ss v ddq v ss v dd v ss v ss v ss a v ss v ss v ss v ddq v ddq nc v ddq v ddq v ddq v ddq a a v dd v ss v dd v ss v ss v ddq v dd v ss v dd v ss v dd v ss v ss v ss v dd v dd v ss v dd v ss v ss nc tck v ss tdi a a dq c v ss dq c v ss dq c dq c nc v ss v ss v ss v ss nc v ss a1 dq d dq d nc nc v ddq v ss tms 891011 a adv a adsc nc oe adsp a nc / 144m v ss v ddq nc dqp b v ddq v dd dq b dq b dq b nc dq b nc dq a dq a v dd v ddq v dd v ddq dq b v dd nc v dd dq a v dd v ddq dq a v ddq v dd v dd v ddq v dd v ddq dq a v ddq a a v ss a a a dq b dq b dq b zz dq a dq a dqp a dq a a v ddq a cy7c1482v33 (4m x 18) a0 a v ss 234 567 1 a b c d e f g h j k l m n p r tdo nc / 288m nc nc nc dqp b nc dq b a ce 1 nc ce 3 bw b bwe a ce2 nc dq b dq b mode nc dq b dq b nc nc nc a a v ddq nc bw a clk gw v ss v ss v ss v ss v ddq v ss v dd v ss v ss v ss a v ss v ss v ss v ss v ddq v ddq nc v ddq v ddq v ddq v ddq a a v dd v ss v dd v ss v ss v ddq v dd v ss v dd v ss v dd v ss v ss v ss v dd v dd v ss v dd v ss v ss nc tck a0 v ss tdi a a dq b v ss nc v ss dq b nc nc v ss v ss v ss v ss nc v ss a1 dq b nc nc nc v ddq v ss tms 891011 a adv a adsc a oe adsp a nc / 144m v ss v ddq nc dqp a v ddq v dd nc dq a dq a nc nc nc dq a nc v dd v ddq v dd v ddq dq a v dd nc v dd nc v dd v ddq dq a v ddq v dd v dd v ddq v dd v ddq nc v ddq a a v ss a a a dq a nc nc zz dq a nc nc dq a a v ddq a
cy7c1480v33 cy7c1482v33 cy7c1486v33 preliminary document #: 38-05283 rev. *c page 6 of 30 pin configurations (continued) 209-ball bga cy7c1486v33 (1m 72) a b c d e f g h j k l m n p r t u v w 123456789 11 10 dq g dq g dq g dq g dq g dq g dq g dq g dq c dq c dq c dq c nc dqp g dq h dq h dq h dq h dq d dq d dq d dq d dqp d dqp c dq c dq c dq c dq c nc dq h dq h dq h dq h dqp h dq d dq d dq d dq d dq b dq b dq b dq b dq b dq b dq b dq b dq f dq f dq f dq f nc dqp f dq a dq a dq a dq a dq e dq e dq e dq e dqp a dqp b dq f dq f dq f dq f nc dq a dq a dq a dq a dqp e dq e dq e dq e dq e aadsp adv a nc nc a aa a a aa aa a a1 a0 a aa aa a nc nc nc gw nc nc bws b bws f bws e bws a bws c bws g bws d bws h tms tdi tdo tck nc nc mode nc v ss v ss nc clk nc v ss v dd v dd v dd v dd v dd v dd v dd v dd v dd v dd v dd v dd v dd v ss v ss v ss v ss v ss v ss v ss v ss nc v dd nc oe ce 3 ce 1 ce 2 adsc bwe v ss v ss v ss v ss v ss v ss v ss zz v ss v ss v ss v ss nc v ddq v ss v ss nc v ss v ssq v ss v ss v ss v ss nc v ss v ddq v ddq v ddq v ddq v ddq nc v ddq v ddq v ddq v ddq nc v ddq v ddq v ddq v ddq nc v ddq v ddq v ddq v ddq v ddq v ddq v ddq v ddq v ddq v ddq
cy7c1480v33 cy7c1482v33 cy7c1486v33 preliminary document #: 38-05283 rev. *c page 7 of 30 pin definitions pin name i/o description a 0 , a 1 , a input- synchronous address inputs used to select one of the address locations . sampled at the rising edge of the clk if adsp or adsc is active low, and ce 1 , ce 2 , and ce 3 are sampled active. a1: a0 are fed to the two-bit counter. bw a ,bw b ,bw c ,bw d , bw e ,bw f ,bw g ,bw h input- synchronous byte write select inputs, active low . qualified with bwe to conduct byte writes to the sram. sampled on the rising edge of clk. gw input- synchronous global write enable input, active low . when asserted low on the rising edge of clk, a global write is conducted (all byte s are written, regardless of the values on bw x and bwe ). bwe input- synchronous byte write enable input, active low . sampled on the rising edge of clk. this signal must be asserted low to conduct a byte write. clk input- clock clock input . used to capture all synchronous i nputs to the device. also used to increment the burst counter when adv is asserted low, during a burst operation. ce 1 input- synchronous chip enable 1 input, active low . sampled on the rising edge of clk. used in conjunction with ce 2 and ce 3 to select/deselec t the device. adsp is ignored if ce 1 is high. ce 2 input- synchronous chip enable 2 input, active high . sampled on the rising edge of clk. used in conjunction with ce 1 and ce 3 to select/desel ect the device. ce 3 input- synchronous chip enable 3 input, active low . sampled on the rising edge of clk. used in conjunction with ce 1 and ce 2 to select/deselect the device. oe input- asynchronous output enable, asynchronous input, active low . controls the direction of the i/o pins. when low, the i/o pins behave as outputs. when deasserted high, i/o pins are tri-stated, and act as input data pins. oe is masked during the first clock of a read cycle when emerging from a deselected state. adv input- synchronous advance input signal, sampled on the rising edge of clk, active low . when asserted, it automatically increm ents the address in a burst cycle. adsp input- synchronous address strobe from processor, sampled on the rising edge of clk, active low . when asserted low, addresses presented to the device are captured in the address registers. a1: a0 are also loaded into the burst counter. when adsp and adsc are both asserted, only adsp is recognized. asdp is ignored when ce 1 is deasserted high. adsc input- synchronous address strobe from controller, sampled on the rising edge of clk, active low . when asserted low, addresses presented to the device are captured in the address registers. a1: a0 are also loaded into the burst counter. when adsp and adsc are both asserted, only adsp is recognized. zz input- asynchronous zz ?sleep? input, active high . when asserted high places the device in a non-time-critical ?sleep? condition with data integrity preserved. for normal operation, this pin has to be low or left floating. zz pin has an internal pull-down. dqs, dqps i/o- synchronous bidirectional data i/o lines . as inputs, they feed into an on-chip data register that is triggered by the rising edge of clk. as output s, they deliver the data contained in the memory location specified by the addresses presented during the previous clock rise of the read cycle. the direction of the pins is controlled by oe . when oe is asserted low, the pins behave as outputs. when high, dqs and dqp x are placed in a tri-state condition. v dd power supply power supply inputs to the core of the device . v ss ground ground for the co re of the device . v ssq i/o ground ground for the i/o circuitry . v ddq i/o power supply power supply for the i/o circuitry . mode input static selects burst order . when tied to gnd selects linear burst sequence. when tied to v dd or left floating selects interleaved burst sequence. this is a strap pin and should remain static during device operation. mode pin has an internal pull-up.
cy7c1480v33 cy7c1482v33 cy7c1486v33 preliminary document #: 38-05283 rev. *c page 8 of 30 functional overview all synchronous inputs pass through input registers controlled by the rising edge of the clock. all data outputs pass through output registers controlled by the rising edge of the clock. maximum access delay from the clock rise (t co ) is 3.0 ns (250-mhz device). the cy7c1480v33/cy7c1482v33/cy7c1486v33 supports secondary cache in systems utilizing either a linear or inter- leaved burst sequence. the interleaved burst order supports pentium and i486 ? processors. the linear burst sequence is suited for processors that utilize a linear burst sequence. the burst order is user selectable, and is determined by sampling the mode input. accesses can be initiated with either the processor address strobe (adsp ) or the controller address strobe (adsc ). address advancement through the burst sequence is controlled by the adv input. a two-bit on-chip wraparound burst counter captures the first address in a burst sequence and automatically increments the address for the rest of the burst access. byte write operations are qualif ied with the byte write enable (bwe ) and byte write select (bw x ) inputs. a global write enable (gw ) overrides all byte write inputs and writes data to all four bytes. all writes are simplified with on-chip synchronous self-timed write circuitry. three synchronous chip selects (ce 1 , ce 2 , ce 3 ) and an asynchronous output enable (oe ) provide for easy bank selection and output tri-state control. adsp is ignored if ce 1 is high. single read accesses this access is initiated when the following conditions are satisfied at cloc k rise: (1) adsp or adsc is asserted low, (2) ce 1 , ce 2 , ce 3 are all asserted active, and (3) the write signals (gw , bwe ) are all deasserted high. adsp is ignored if ce 1 is high. the address presented to the address inputs (a) is stored into the address advancement logic and the address register while being presented to the memory array. the corresponding data is allowed to propagate to the input of the output registers. at the ri sing edge of the next clock the data is allowed to propagate through the output register and onto the data bus within 3.0 ns (250-mhz device) if oe is active low. the only exception occurs when the sram is emerging from a deselected state to a selected state, its outputs are always tri-stated during the first cycle of the access. after the first cycle of the access, the outputs are controlled by the oe signal. consecutive single read cycles are supported. once the sram is deselected at clock rise by the chip select and either adsp or adsc signals, its output will tri-state immediately. single write accesses initiated by adsp this access is initiated when both of the following conditions are satisfied at cl ock rise: (1) adsp is asserted low, and (2) ce 1 , ce 2 , ce 3 are all asserted active. the address presented to a is loaded into the address register and the address advancement logic while being delivered to the memory array. the write signals (gw , bwe , and bw x ) and adv inputs are ignored during this first cycle. adsp -triggered write accesses require two clock cycles to complete. if gw is asserted low on the second clock rise, the data presented to the dqs inputs is written into the corre- sponding address location in the memory array. if gw is high, then the write operation is controlled by bwe and bw x signals. the cy7c1480v33/cy7c1482v 33/cy7c1486v33 provides byte write capability that is described in the write cycle descriptions table. asserting the byte write enable input (bwe ) with the selected byte write (bw x ) input, will selec- tively write to only the desired bytes. bytes not selected during a byte write operation will remain unaltered. a synchronous self-timed write mechanism has been provided to simplify the write operations. because cy7c1480v33/cy7c1482v33/cy7c1486v33 is a common i/o device, the output enable (oe ) must be deasserted high before presenting data to the dqs inputs. doing so will tri-state the output drivers. as a safety precaution, dqs are automatical ly tri-stated whenever a write cycle is detected, regardle ss of the state of oe . single write accesses initiated by adsc adsc write accesses are initiated when the following condi- tions are satisfied: (1) adsc is asserted low, (2) adsp is deasserted high, (3) ce 1 , ce 2 , ce 3 are all asserted active, and (4) the appropriate combinat ion of the write inputs (gw , bwe , and bw x ) are asserted active to conduct a write to the desired byte(s). adsc -triggered write accesses require a single clock cycle to complete. the address presented to a is loaded into the address register and the address advancement logic while being delivered to the memory array. tdo jtag serial output synchronous serial data-out to the jtag circuit . delivers data on the negative edge of tck. if the jtag feature is not being utilized, this pi n should be disconnected. this pin is not available on tqfp packages. tdi jtag serial input synchronous serial data-in to the jtag circuit . sampled on the rising edge of tck. if the jtag feature is not being utilize d, this pin can be discon nected or connected to v dd . this pin is not available on tqfp packages. tms jtag serial input synchronous serial data-in to the jtag circuit . sampled on the rising edge of tck. if the jtag feature is not being utilize d, this pin can be discon nected or connected to v dd . this pin is not available on tqfp packages. tck jtag clock clock input to the jtag circuitry . if the jtag feature is not being utilized, this pin must be connected to v ss . this pin is not available on tqfp packages. nc - no connects . not internally connected to the die pin definitions (continued) pin name i/o description
cy7c1480v33 cy7c1482v33 cy7c1486v33 preliminary document #: 38-05283 rev. *c page 9 of 30 the adv input is ignored during this cycle. if a global write is conducted, the data presented to the dqs is written into the corresponding address location in the memory core. if a byte write is conducted, only the se lected bytes are written. bytes not selected during a byte write operation will remain unaltered. a synchronous self-timed write mechanism has been provided to simplify the write operations. because cy7c1480v33/cy7c1482v33/cy7c1486v33 is a common i/o device, the output enable (oe ) must be deasserted high before presenting data to the dqs inputs. doing so will tri-state the output drivers. as a safety precaution, dqs are automatically tri-stated whenever a write cycle is detected, regard less of the state of oe . burst sequences the cy7c1480v33/cy7c1482v33/cy7c1486v33 provides a two-bit wraparound counter, fed by a1: a0, that implements either an interleaved or linear burst sequence. the interleaved burst sequence is designed specifically to support intel pentium applications. the linear burst sequence is designed to support processors that foll ow a linear burst sequence. the burst sequence is user select able through the mode input. asserting adv low at clock rise will automatically increment the burst counter to the next address in the burst sequence. both read and write burst operations are supported. sleep mode the zz input pin is an asynchronous input. asserting zz places the sram in a power conservation ?sleep? mode. two clock cycles are required to enter into or exit from this ?sleep? mode. while in this mode, da ta integrity is guaranteed. accesses pending when entering the ?sleep? mode are not considered valid nor is the completion of the operation guaranteed. the device must be deselected prior to entering the ?sleep? mode. ce 1 , ce 2 , ce 3 , adsp , and adsc must remain inactive for the duration of t zzrec after the zz input returns low. interleaved burst address table (mode = floating or v dd ) first address a1: a0 second address a1: a0 third address a1: a0 fourth address a1: a0 00 01 10 11 01 00 11 10 10 11 00 01 11 10 01 00 linear burst address table (mode = gnd) first address a1: a0 second address a1: a0 third address a1: a0 fourth address a1: a0 00 01 10 11 01 10 11 00 10 11 00 01 11 00 01 10 zz mode electrical characteristics parameter description test conditions min. max. unit i ddzz sleep mode standby current zz > v dd ? 0.2v 120 ma t zzs device operation to zz zz > v dd ? 0.2v 2t cyc ns t zzrec zz recovery time zz < 0.2v 2t cyc ns t zzi zz active to sleep current this parameter is sampled 2t cyc ns t rzzi zz inactive to exit sleep current this parameter is sampled 0 ns
cy7c1480v33 cy7c1482v33 cy7c1486v33 preliminary document #: 38-05283 rev. *c page 10 of 30 truth table [ 2, 3, 4, 4, 5, 6] operation add. used ce 1 ce 2 ce 3 zz adsp adsc adv write oe clk dq deselect cycle, power down none h x x l x l x x x l-h tri-state deselect cycle, po wer down none l l x l l x x x x l-h tri-state deselect cycle, power down none l x h l l x x x x l-h tri-state deselect cycle, power down none l l x l h l x x x l-h tri-state deselect cycle, power down none l x h l h l x x x l-h tri-state sleep mode, power down none x x x h x x x x x x tri-state read cycle, begin burst external l h l l l x x x l l-h q read cycle, begin burst external l h l l l x x x h l-h tri-state write cycle, begin burst external l h l l h l x l x l-h d read cycle, begin burst external l h l l h l x h l l-h q read cycle, begin burst external l h l l h l x h h l-h tri-state read cycle, continue burst next x x x l h h l h l l-h q read cycle, continue burst next x x x l h h l h h l-h tri-state read cycle, continue burst next h x x l x h l h l l-h q read cycle, continue burst next h x x l x h l h h l-h tri-state write cycle, continue burst next x x x l h h l l x l-h d write cycle, continue burst next h x x l x h l l x l-h d read cycle, suspend burst current x x x l h h h h l l-h q read cycle, suspend burst current x x x l h h h h h l-h tri-state read cycle, suspend burst current h x x l x h h h l l-h q read cycle, suspend burst current h x x l x h h h h l-h tri-state write cycle,suspend burst current x x x l h h h l x l-h d write cycle,suspend burst current h x x l x h h l x l-h d notes: 2. x = ?don't care.? h = logic high, l = logic low. 3. write = l when any one or more byte write enable signals and bwe = l or gw = l. write = h when all byte write enable signals, bwe , gw = h. 4. the dq pins are controlled by the current cycle and the oe signal. oe is asynchronous and is not sampled with the clock. 5. the sram always initiates a read cycle when adsp is asserted, regardless of the state of gw , bwe , or bw x . writes may occur only on subsequent clocks after the adsp or with the assertion of adsc . as a result, oe must be driven high prior to the start of the write cycle to allow the outputs to tri-state. oe is a don't care for the remainder of the write cycle 6. oe is asynchronous and is not sampled with the clock rise. it is masked internally during write cycles. during a read cycle all d ata bits are tri-state when oe is inactive or when the device is deselect ed, and all data bits behave as output when oe is active (low). 7. bw x represents any byte write sign al.to enable any byte write bw x, a logic low signal should be applied at clock rise. any number of byte writes can be enabled at the same time for any given write.
cy7c1480v33 cy7c1482v33 cy7c1486v33 preliminary document #: 38-05283 rev. *c page 11 of 30 truth table for read/write [4] function (cy7c1480v33) gw bwe bw d bw c bw b bw a read hhxxxx read hlhhhh write byte a ? (dq a and dqp a ) hlhhhl write byte b ? (dq b and dqp b )hlhhlh write bytes b, a h l h h l l write byte c ? (dq c and dqp c ) hlhlhh write bytes c, a h l h l h l write bytes c, b h l h l l h write bytes c, b, a h l h l l l write byte d ? (dq d and dqp d ) hl lhhh write bytes d, a h l l h h l write bytes d, b h l l h l h write bytes d, b, a h l l h l l write bytes d, c h l l l h h write bytes d, c, a h l l l h l write bytes d, c, b hllllh write all bytes hlllll write all bytes lxxxxx truth table for read/write [4] function (cy7c1482v33) gw bwe bw b bw a read h h x x read h l h h write byte a ? (dq a and dqp a )hlhl write byte b ? (dq b and dqp b )hllh write bytes b, a h l l l write all bytes h l l l write all bytes l x x x
cy7c1480v33 cy7c1482v33 cy7c1486v33 preliminary document #: 38-05283 rev. *c page 12 of 30 ieee 1149.1 serial boundary scan (jtag) the cy7c1480v33/cy7c1482v3 3 incorporates a serial boundary scan test access port (tap). this port operates in accordance with ieee standard 1149.1-1990 but does not have the set of functions required for full 1149.1 compliance. these functions from the i eee specification are excluded because their inclusion places an added delay in the critical speed path of the sram. note that the tap controller functions in a manner that does not conflict with the operation of other devices using 1149.1 fully compliant taps. the tap operates using jedec-standard 3. 3v or 2.5v i/o logic levels. the cy7c1480v33/cy7c1482v33 contains a tap controller, instruction register, boundary sc an register, bypass register, and id register. disabling the jtag feature it is possible to operate the sram without using the jtag feature. to disable the tap controller, tck must be tied low (v ss ) to prevent clocking of the device. tdi and tms are inter- nally pulled up and may be unconnected. they may alternately be connected to v dd through a pull-up resistor. tdo should be left unconnected. upon power-up, the device will come up in a reset state which will not interfere with the operation of the device. tap controller state diagram the 0/1 next to each state repr esents the value of tms at the rising edge of tck. test access port (tap) test clock (tck) the test clock is used only with the tap controller. all inputs are captured on the rising edge of tck. all outputs are driven from the falling edge of tck. test mode select (tms) the tms input is used to give commands to the tap controller and is sampled on the rising edge of tck. it is allowable to leave this ball unconnected if the tap is not used. the ball is pulled up internally, resulting in a logic high level. test data-in (tdi) the tdi ball is used to serially input information into the registers and can be connected to the input of any of the registers. the register between tdi and tdo is chosen by the instruction that is loaded into the tap instruction register. for information on loading the instruction register, see the tap controller state diagram. tdi is internally pulled up and can be unconnected if the tap is unused in an application. tdi is connected to the most significant bit (msb) of any register. (see tap controller block diagram.) test data-out (tdo) the tdo output ball is used to serially clock data-out from the registers. the output is active depending upon the current state of the tap state machine. the output changes on the falling edge of tck. tdo is connected to the least significant bit (lsb) of any register. (see tap controller state diagram.) tap controller block diagram performing a tap reset a reset is performed by forcing tms high (v dd ) for five rising edges of tck. this reset does not affect the operation of the sram and may be performed while the sram is operating. at power-up, the tap is reset internally to ensure that tdo comes up in a high-z state. tap registers registers are connected between the tdi and tdo balls and allow data to be scanned into and out of the sram test circuitry. only one register can be selected at a time through the instruction register. data is serially loaded into the tdi ball on the rising edge of tck. data is output on the tdo ball on the falling edge of tck. test-logic reset run-test/ idle select dr-scan select ir-scan capture-dr shift-dr capture-ir shift-ir exit1-dr pause-dr exit1-ir pause-ir exit2-dr update-dr exit2-ir update-ir 1 1 1 0 1 1 0 0 1 1 1 0 0 0 0 0 0 0 0 0 1 0 1 1 0 1 0 1 1 1 1 0 bypass register 0 instruction register 0 1 2 identification register 0 1 2 29 30 31 . . . boundary scan register 0 1 2 . . x . . . s election circuitr y selection circuitry tck t ms tap controller tdi td o
cy7c1480v33 cy7c1482v33 cy7c1486v33 preliminary document #: 38-05283 rev. *c page 13 of 30 instruction register three-bit instructions can be serially loaded into the instruction register. this register is loaded when it is placed between the tdi and tdo balls as shown in the tap controller block diagram. upon power-up, the instruction register is loaded with the idcode instruction. it is also loaded with the idcode instruction if the controller is placed in a reset state as described in the previous section. when the tap controller is in the capture-ir state, the two least significant bits are loaded with a binary ?01? pattern to allow for fault isolation of the board-level serial test data path. bypass register to save time when serially shifting data through registers, it is sometimes advantageous to skip certain chips. the bypass register is a single-bit register that can be placed between the tdi and tdo balls. this allows data to be shifted through the sram with minimal delay. the bypass register is set low (v ss ) when the bypass instruction is executed. boundary scan register the boundary scan register is connected to all the input and bidirectional balls on the sram. the x36 configuration has a 73-bit-long register, and t he x18 configuration has a 54-bit-long register. the boundary scan register is lo aded with the contents of the ram i/o ring when the tap controller is in the capture-dr state and is then placed between the tdi and tdo balls when the controller is moved to the shift-dr state. the extest, sample/preload and sample z instructions can be used to capture the contents of the i/o ring. the boundary scan order tables show the order in which the bits are connected. each bit corresponds to one of the bumps on the sram package. the msb of the register is connected to tdi and the lsb is connected to tdo. identification (id) register the id register is loaded with a vendor-specific, 32-bit code during the capture-dr state when the idcode command is loaded in the instruction regi ster. the idcode is hardwired into the sram and can be shifted out when the tap controller is in the shift-dr state. the id register has a vendor code and other information described in the identification register definitions table. tap instruction set overview eight different instructions are possible with the three-bit instruction register. all combinations are listed in the instruction codes table. three of these instructions are listed as reserved and should not be used. the other five instruc- tions are described in detail below. the tap controller used in this sram is not fully compliant to the 1149.1 convention because some of the mandatory 1149.1 instructions are not fully implemented. the tap controller cannot be used to load address data or control signals into the sram and cannot preload the i/o buffers. the sram does not implement the 1149.1 commands extest or intest or the preload portion of sample/preload; rather, it per forms a capture of the i/o ring when these instructions are executed. instructions are loaded into the tap controller during the shift-ir state when the instruction register is placed between tdi and tdo. during this stat e, instructions are shifted through the instruction register through the tdi and tdo balls. to execute the instruction once it is shifted in, the tap controller needs to be moved into the update-ir state. extest extest is a mandatory 1149.1 instruction which is to be executed whenever the instructi on register is loaded with all 0s. extest is not implemented in this sram tap controller, and therefore this device is not compliant to 1149.1. the tap controller does recognize an all-0 instruction. when an extest instruction is loaded into the instruction register, the sram responds as if a sample/preload instruction has been loaded. there is one difference between the two instructions. un like the sample/preload instruction, extest places the sram outputs in a high-z state. idcode the idcode instruction causes a vendor-specific, 32-bit code to be loaded into the instruction register. it also places the instruction register between the tdi and tdo balls and allows the idcode to be shifted out of the device when the tap controller enters the shift-dr state. the idcode instruction is loaded into the instruction register upon power-up or whenever the tap controller is given a test logic reset state. sample z the sample z instruction causes the boundary scan register to be connected between the tdi and tdo balls when the tap controller is in a shift-dr state. it also places all sram outputs into a high-z state. sample/preload sample/preload is a 1149.1 m andatory instruction. the preload portion of this instru ction is not implemented, so the device tap controller is not fully 1149.1 compliant. when the sample/preload instruction is loaded into the instruction register and the tap controller is in the capture-dr state, a snapshot of data on the inputs and bidirectional balls is captured in the boundary scan register. the user must be aware that th e tap controller clock can only operate at a frequency up to 10 mhz, while the sram clock operates more than an order of magnitude faster. because there is a large difference in the clock frequencies, it is possible that during the capture-dr state, an input or output will undergo a transition. the ta p may then try to capture a signal while in transition (metastable state). this will not harm the device, but there is no guar antee as to the value that will be captured. repeatable results may not be possible. to guarantee that the boundary scan register will capture the correct value of a signal, the sram signal must be stabilized long enough to meet the tap controller?s capture set-up plus hold time (t cs plus t ch ). the sram clock input might not be captured correctly if there is no way in a design to stop (or slow) the clock during a sample/preload instruction. if th is is an issue, it is still
cy7c1480v33 cy7c1482v33 cy7c1486v33 preliminary document #: 38-05283 rev. *c page 14 of 30 possible to capture all other signals and simply ignore the value of the clk captured in the boundary scan register. once the data is captured, it is possible to shift out the data by putting the tap into the shift-dr state. this places the boundary scan register between the tdi and tdo balls. note that since the preload part of the command is not implemented, putting the tap to the update-dr state while performing a sample/preload instruction will have the same effect as the pause-dr command. bypass when the bypass instruction is loaded in t he instruction register and the tap is placed in a shift-dr state, the bypass register is placed between the tdi and tdo balls. the advantage of the bypass instructio n is that it shortens the boundary scan path when multiple devices are connected together on a board. reserved these instructions are not im plemented but are reserved for future use. do not use these instructions. tap timing tap ac switching characteristics over the operating range [ 8 , 9 ] parameter description min. max. unit clock t tcyc tck clock cycle time 50 ns t tf tck clock frequency 20 mhz t th tck clock high time 25 ns t tl tck clock low time 25 ns output times t tdov tck clock low to tdo valid 5 ns t tdox tck clock low to tdo invalid 0 ns set-up times t tmss tms set-up to tck clock rise 5 ns t tdis tdi set-up to tck clock rise 5 ns t cs capture set-up to tck rise 5 ns hold times t tmsh tms hold after tck clock rise 5 ns t tdih tdi hold after clock rise 5 ns t ch capture hold after clock rise 5 ns notes: 8. t cs and t ch refer to the set-up and hold time requirements of latching data from the boundary scan register. 9. test conditions are specified using t he load in tap ac test conditions. t r /t f = 1 ns. t tl test clock (tck) 123456 t est mode select (tms) t th test data-out (tdo) t cyc test data-in (tdi) t tmsh t tmss t tdih t tdis t tdox t tdov don?t care undefined
cy7c1480v33 cy7c1482v33 cy7c1486v33 preliminary document #: 38-05283 rev. *c page 15 of 30 3.3v tap ac test conditions input pulse levels ............................................... .v ss to 3.3v input rise and fall times ......... .......................................... 1 ns input timing referenc e levels ...........................................1.5v output reference levels...................................................1.5v test load termination supply vo ltage...............................1.5v 3.3v tap ac output load equivalent 2.5v tap ac test conditions input pulse levels................................................. v ss to 2.5v input rise and fall time .....................................................1 ns input timing reference levels... ...................................... 1.25v output reference levels .......... ...................................... 1.25v test load termination supply voltage ............................ 1.25v 2.5v tap ac output load equivalent t do 1.5v 20p f z = 50 ? o 50 ? t do 1.25v 20p f z = 50 ? o 50 ? tap dc electrical characteristics and operating conditions (0c < t a < +70c; v dd = 3.135 to 3.6v un less otherwise noted) [10] parameter description test conditions min. max. unit v oh1 output high voltage i oh = ?4.0 ma, v ddq = 3.3v 2.4 v i oh = ?1.0 ma, v ddq = 2.5v 2.0 v v oh2 output high voltage i oh = ?100 a v ddq = 3.3v 2.9 v v ddq = 2.5v 2.1 v v ol1 output low voltage i ol = 8.0 ma v ddq = 3.3v 0.4 v i ol = 1.0 ma v ddq = 2.5v 0.4 v v ol2 output low voltage i ol = 100 a v ddq = 3.3v 0.2 v v ddq = 2.5v 0.2 v v ih input high voltage v ddq = 3.3v 2.0 v dd + 0.3 v v ddq = 2.5v 1.7 v dd + 0.3 v v il input low voltage v ddq = 3.3v ?0.3 0.8 v v ddq = 2.5v ?0.3 0.7 v i x input load current gnd < v in < v ddq ?5 5 a identification register definitions instruction field cy7c1480v33 (2m x36) cy7c1482v33 (4m x 18) cy7c1486v33 (1m x72) description revision number (31:29) 000 000 000 describes the version number device depth (28:24) 01011 01011 01011 reserved for internal use architecture/memory type(23:18) 000000 000000 0000 00 defines memory type and architecture bus width/density(17:12) 100100 010100 110100 defines width and density cypress jedec id code (11:1) 00000110100 00000110100 000 00110100 allows unique identification of sram vendor id register presence indicator (0) 1 1 1 indicates the presence of an id register notes: 10. all voltages referenced to v ss (gnd). 11. bit #24 is ?1? in the id register definition s for both 2.5v and 3.3v ve rsions of this device.
cy7c1480v33 cy7c1482v33 cy7c1486v33 preliminary document #: 38-05283 rev. *c page 16 of 30 scan register sizes register name bit size (x36) b it size (x18) bit size (x72) instruction 3 3 3 bypass 1 1 1 id 32 32 32 boundary scan order-165fbga 73 54 - boundary scan order-209bga - - 112 identification codes instruction code description extest 000 captures the i/o ring contents. idcode 001 loads the id register with the vendor id code and places the register between tdi and tdo. this operation does not affect sram operations. sample z 010 captures i/o ring contents. plac es the boundary scan register between tdi and tdo. forces all sram output drivers to a high-z state. reserved 011 do not use: this instruct ion is reserved for future use. sample/preload 100 captures i/o ring contents. pl aces the boundary scan regi ster between tdi and tdo. does not affect sram operation. reserved 101 do not use: this instruct ion is reserved for future use. reserved 110 do not use: this instruct ion is reserved for future use. bypass 111 places the bypass register between tdi and tdo. this operation does not affect sram operations. boundary scan order (x36) bit # 165-ball id 1c1 2d1 3e1 4d2 5e2 6f1 7g1 8f2 9g2 10 j1 11 k1 12 l1 13 j2 14 m1 15 n1 16 k2 17 l2 18 m2 19 r1 20 r2 21 r3 22 p2 23 r4 24 p6 25 r6 26 n6 27 p11 28 r8 29 p3 30 p4 31 p8 32 p9 33 p10 34 r9 35 r10 36 r11 37 n11 38 m11 39 l11 40 m10 41 l10 42 k11 43 j11 44 k10 45 j10 46 h11 47 g11 48 f11 49 e11 50 d10 boundary scan order (x36) (continued) bit # 165-ball id
cy7c1480v33 cy7c1482v33 cy7c1486v33 preliminary document #: 38-05283 rev. *c page 17 of 30 51 d11 52 c11 53 g10 54 f10 55 e10 56 a10 57 b10 58 a9 59 b9 60 a8 61 b8 62 a7 63 b7 64 b6 65 a6 66 b5 67 a5 68 a4 69 b4 70 b3 71 a3 72 a2 73 b2 boundary scan order (x18) bit # 165-ball id 1d2 2e2 3f2 4g2 5j1 6k1 7l1 8m1 9n1 10 r1 11 r2 12 r3 13 p2 14 r4 15 p6 16 r6 17 n6 18 p11 19 r8 20 p3 21 p4 22 p8 23 p9 24 p10 boundary scan order (x36) (continued) bit # 165-ball id 25 r9 26 r10 27 r11 28 m10 29 l10 30 k10 31 j10 32 h11 33 g11 34 f11 35 e11 36 d11 37 c11 38 a11 39 a10 40 b10 41 a9 42 b9 43 a8 44 b8 45 a7 46 b7 47 b6 48 a6 49 b5 50 a4 51 b3 52 a3 53 a2 54 b2 boundary scan exit order (x72) bit # 209-ball id 1a1 2a2 3b1 4b2 5c1 6c2 7d1 8d2 9e1 10 e2 11 f1 12 f2 13 g1 14 g2 15 h1 16 h2 17 j1 boundary scan order (x18) (continued) bit # 165-ball id
cy7c1480v33 cy7c1482v33 cy7c1486v33 preliminary document #: 38-05283 rev. *c page 18 of 30 18 j2 19 l1 20 l2 21 m1 22 m2 23 n1 24 n2 25 p1 26 p2 27 r2 28 r1 29 t1 30 t2 31 u1 32 u2 33 v1 34 v2 35 w1 36 w2 37 t6 38 v3 39 v4 40 u4 41 w5 42 v6 43 w6 44 u3 45 u9 46 v5 47 u5 48 u6 49 w7 50 v7 51 u7 52 v8 53 v9 54 w11 55 w10 56 v11 57 v10 58 u11 59 u10 60 t11 61 t10 62 r11 63 r10 64 p11 65 p10 66 n11 67 n10 boundary scan exit order (x72) (continued) bit # 209-ball id 68 m11 69 m10 70 l11 71 l10 72 p6 73 j11 74 j10 75 h11 76 h10 77 g11 78 g10 79 f11 80 f10 81 e10 82 e11 83 d11 84 d10 85 c11 86 c10 87 b11 88 b10 89 a11 90 a10 91 a9 92 u8 93 a7 94 a5 95 a6 96 d6 97 b6 98 d7 99 k3 100 a8 101 b4 102 b3 103 c3 104 c4 105 c8 106 c9 107 b9 108 b8 109 a4 110 c6 111 b7 112 a3 boundary scan exit order (x72) (continued) bit # 209-ball id
cy7c1480v33 cy7c1482v33 cy7c1486v33 preliminary document #: 38-05283 rev. *c page 19 of 30 maximum ratings (above which the useful life may be impaired. for user guide- lines, not tested.) storage temperature ................................. ?65 c to +150 c ambient temperature with power applied............................................. ?55 c to +125 c supply voltage on v dd relative to gnd........ ?0.3v to +4.6v dc voltage applied to outputs in tri-state........................................... ?0.5v to v ddq + 0.5v dc input voltage....................................?0.5v to v dd + 0.5v current into outputs (low).... ..................................... 20 ma static discharge voltage......... ........... ............ ........... >2001v (per mil-std-883, method 3015) latch-up current..................................................... >200 ma operating range range ambient temperature v dd v ddq commercial 0c to +70c 3.3v ? 5%/+10% 2.5v ? 5% to v dd electrical characteristics over the operating range [12, 13] parameter description test conditions min. max. unit v dd power supply voltage 3.135 3.6 v v ddq i/o supply voltage v ddq = 3.3v 3.135 v dd v v ddq = 2.5v 2.375 2.625 v v oh output high voltage v ddq = 3.3v, v dd = min., i oh = ?4.0 ma 2.4 v v ddq = 2.5v, v dd = min., i oh = ?1.0 ma 2.0 v v ol output low voltage v ddq = 3.3v, v dd = min., i ol = 8.0 ma 0.4 v v ddq = 2.5v, v dd = min., i ol = 1.0 ma 0.4 v v ih input high voltage [12] v ddq = 3.3v 2.0 v dd + 0.3v v v ddq = 2.5v 1.7 v dd + 0.3v v v il input low voltage [12] v ddq = 3.3v ?0.3 0.8 v v ddq = 2.5v ?0.3 0.7 v i x input load current except zz and mode gnd v i v ddq ?5 5 a input current of mode input = v ss ?5 a input = v dd 30 a input current of zz input = v ss ?30 a input = v dd 5 a i oz output leakage current gnd v i v ddq, output disabled ?5 5 a i dd v dd operating supply current v dd = max., i out = 0 ma, f = f max = 1/t cyc 4.0-ns cycle, 250 mhz 500 ma 5.0-ns cycle, 200 mhz 500 ma 6.0-ns cycle, 167 mhz 450 ma i sb1 automatic ce power-down current?ttl inputs v dd = max, device deselected, v in v ih or v in v il f = f max = 1/t cyc 4.0-ns cycle, 250 mhz 245 ma 5.0-ns cycle, 200 mhz 245 ma 6.0-ns cycle, 167 mhz 245 ma i sb2 automatic ce power-down current?cmos inputs v dd = max, device deselected, v in 0.3v or v in > v ddq ? 0.3v, f = 0 all speeds 120 ma i sb3 automatic ce power-down current?cmos inputs v dd = max, device deselected, or v in 0.3v or v in > v ddq ? 0.3v f = f max = 1/t cyc 4.0-ns cycle, 250 mhz 245 ma 5.0-ns cycle, 200 mhz 245 ma 6.0-ns cycle, 167 mhz 245 ma i sb4 automatic ce power-down current?ttl inputs v dd = max, device deselected, v in v ih or v in v il , f = 0 all speeds 135 ma shaded areas contain advance information. notes: 12. overshoot: v ih (ac) < v dd +1.5v (pulse width less than t cyc /2), undershoot: v il (ac) > ?2v (pulse width less than t cyc /2). 13. power-up: assumes a linear ramp from 0v to v dd (min.) within 200 ms. during this time v ih < v dd and v ddq < v dd\
cy7c1480v33 cy7c1482v33 cy7c1486v33 preliminary document #: 38-05283 rev. *c page 20 of 30 thermal resistance [14] parameter description test conditions tqfp package 209-bga package fbga package unit ja thermal resistance (junction to ambient) test conditions follow standard test methods and procedures for measuring thermal impedance, per eia / jesd51. 24.63 15.2 16.3 c/w jc thermal resistance (junction to case) 2.28 1.7 2.1 c/w capacitance [14] parameter description test conditions tqfp max. 209-bga max. 165-fbga max. unit c address address input capacitance t a = 25 c, f = 1 mhz, v dd = 3.3v v ddq = 2.5v 666pf c data data input capacitance 5 5 5 pf c ctrl control input capacitance 8 8 8 pf c clk clock input capacitance 6 6 6 pf c i/o input/output capacitance 5 5 5 pf ac test loads and waveforms note: 14. tested initially and after any design or process change that may affect these parameters. output r = 317 ? r = 351 ? 5pf including jig and scope (a) (b) output r l = 50 ? z 0 = 50 ? v l = 1.5v 3.3v all input pulses v ddq gnd 90% 10% 90% 10% 1ns 1ns (c) output r = 1667 ? r =1538 ? 5pf including jig and scope (a) (b) output r l = 50 ? z 0 = 50 ? v l = 1.25v 2.5v all input pulses v ddq gnd 90% 10% 90% 10% 1ns 1ns (c) 3.3v i/o test load 2.5v i/o test load
cy7c1480v33 cy7c1482v33 cy7c1486v33 preliminary document #: 38-05283 rev. *c page 21 of 30 switching characteristics over the operating range [19, 20] parameter description 250 mhz 200 mhz 167 mhz unit min. max. min. max. min. max. t power v dd (typical) to the first access [15] 1 1 1 ms clock t cyc clock cycle time 4.0 5.0 6.0 ns t ch clock high 2.0 2.0 2.4 ns t cl clock low 2.0 2.0 2.4 ns output times t co data output valid after clk rise 3.0 3.0 3.4 ns t doh data output hold after clk rise 1.3 1.3 1.5 ns t clz clock to low-z [16, 17, 18] 1.3 1.3 1.5 ns t chz clock to high-z [16, 17, 18] 3.0 3.0 3.4 ns t oev oe low to output valid 3.0 3.0 3.4 ns t oelz oe low to output low-z [16, 17, 18] 0 0 0 ns t oehz oe high to output high-z [16, 17, 18] 3.0 3.0 3.4 ns set-up times t as address set-up before clk rise 1.4 1.4 1.5 ns t ads adsc , adsp set-up before clk rise 1.4 1.4 1.5 ns t advs adv set-up before clk rise 1.4 1.4 1.5 ns t wes gw , bwe , bw x set-up before clk rise 1.4 1.4 1.5 ns t ds data input set-up before clk rise 1.4 1.4 1.5 ns t ces chip enable set-up before clk rise 1.4 1.4 1.5 ns hold times t ah address hold after clk rise 0.4 0.4 0.5 ns t adh adsp , adsc hold after clk rise 0.4 0.4 0.5 ns t advh adv hold after clk rise 0.4 0.4 0.5 ns t weh gw , bwe , bw x hold after clk rise 0.4 0.4 0.5 ns t dh data input hold after clk rise 0.4 0.4 0.5 ns t ceh chip enable hold after clk rise 0.4 0.4 0.5 ns shaded areas contain advance information. notes: 15. this part has a voltage regulator internally; t power is the time that the power needs to be supplied above v dd (minimum) initially before a read or write operation can be initiated. 16. t chz , t clz ,t oelz , and t oehz are specified with ac test conditions shown in part (b) of ac test loads. transition is measured 200 mv from steady-state vo ltage. 17. at any given voltage and temperature, t oehz is less than t oelz and t chz is less than t clz to eliminate bus contention between srams when sharing the same data bus. these specifications do not imply a bus contention condition, but refl ect parameters guaranteed over worst case user conditions. device is designed to achieve high-z prior to low-z under the same system conditions 18. this parameter is sampled and not 100% tested. 19. timing reference level is 1.5v when v ddq = 3.3v and is 1.25v when v ddq = 2.5v. 20. test conditions shown in (a) of ac test loads unless otherwise noted.
cy7c1480v33 cy7c1482v33 cy7c1486v33 preliminary document #: 38-05283 rev. *c page 22 of 30 switching waveforms read cycle timing [21] note: 21. on this diagram, when ce is low: ce 1 is low, ce 2 is high and ce 3 is low. when ce is high: ce 1 is high or ce 2 is low or ce 3 is high. t cyc t cl clk adsp t adh t ads address t ch oe adsc ce t ah t as a1 t ceh t ces gw, bwe, bwx d ata out (q) high-z t clz t doh t co adv t oehz t co single read burst read t oev t oelz t chz adv suspends burst. burst wraps around to its initial state t advh t advs t weh t wes t adh t ads q(a2) q(a2 + 1) q(a2 + 2) q(a1) q(a2) q(a2 + 1) q(a2 + 3) a2 a3 deselect cycle burst continued with new base address don?t care undefined
cy7c1480v33 cy7c1482v33 cy7c1486v33 preliminary document #: 38-05283 rev. *c page 23 of 30 write cycle timing [21, 22] note: 22. full width write can be initiated by either gw low; or by gw high, bwe low and bw x low. switching waveforms (continued) t cyc t cl clk adsp t adh t ads address t ch oe adsc ce t ah t as a1 t ceh t ces bwe, bw x d ata out (q) high-z adv burst read burst write d(a2) d(a2 + 1) d(a2 + 1) d(a1) d(a3) d(a3 + 1) d(a3 + 2) d(a2 + 3) a2 a3 data in (d) extended burst write d(a2 + 2) single write t adh t ads t adh t ads t oehz t advh t advs t weh t wes t dh t ds gw t weh t wes byte write signals are ignored for first cycle when adsp initiates burst adsc extends burst adv suspends burst don?t care undefined
cy7c1480v33 cy7c1482v33 cy7c1486v33 preliminary document #: 38-05283 rev. *c page 24 of 30 read/write cycle timing [21, 23, 24] notes: 23. the data bus (q) remains in high-z following a write cycle, unless a new read access is initiated by adsp or adsc . 24. gw is high. switching waveforms (continued) t cyc t cl clk adsp t adh t ads address t ch oe adsc ce t ah t as a2 t ceh t ces bwe, bw x d ata out (q) high-z adv single write d(a3) a4 a5 a6 d(a5) d(a6) data in (d) burst read back-to-back reads high-z q(a2) q(a1) q(a4) q(a4+1) q(a4+2) t weh t wes q(a4+3) t oehz t dh t ds t oelz t clz t co back-to-back writes a1 don?t care undefined a3
cy7c1480v33 cy7c1482v33 cy7c1486v33 preliminary document #: 38-05283 rev. *c page 25 of 30 zz mode timing [27, 28] notes: 25. device must be deselected when entering zz mode. see cycle descr iptions table for all possible signal conditions to deselect the device. 26. dqs are in high-z when exiting zz sleep mode. switching waveforms (continued) t zz i supply clk zz t zzrec a ll inputs (except zz) don?t care i ddzz t zzi t rzzi outputs (q) high-z deselect or read only
cy7c1480v33 cy7c1482v33 cy7c1486v33 preliminary document #: 38-05283 rev. *c page 26 of 30 ordering information speed (mhz) ordering code package name part and package type operating range 250 cy7c1480v33-250axc cy7c1482v33-250axc a101 lead-free 100-lead 14 20 1.4 mm thin quad flat pack commercial cy7c1486v33-250bgc bb209a 209-ball bga (14 22 1.76 mm) cy7c1480v33-250bzc cy7c1482v33-250bzc bb165c 165 fbga(15 x 17 x1.4 mm) cy7c1486v33-250bgxc bb209a lead-free 209-ball bga (14 22 1.76 mm) cy7c1480v33-250bzxc cy7c1482v33-250bzxc bb165c lead-free 165 fbga(15 x 17 x1.4 mm) 200 cy7c1480v33-200axc cy7c1482v33-200axc a101 lead-free 100-lead 14 20 1.4 mm thin quad flat pack cy7c1486v33-200bgc bb209a 209-ball bga (14 22 1.76 mm) cy7c1480v33-200bzc cy7c1482v33-200bzc bb165c 165 fbga(15 x 17 x1.4 mm) cy7c1486v33-200bgxc bb209a lead-free 209-ball bga (14 22 1.76 mm) cy7c1480v33-200bzxc cy7c1482v33-200bzxc bb165c lead-free 165 fbga(15 x 17 x1.4 mm) 167 cy7c1480v33-167axc cy7c1482v33-167axc a101 lead-free 100-lead 14 20 1.4 mm thin quad flat pack cy7c1486v33-167bgc bb209a 209-ball bga (14 22 1.76 mm) cy7c1480v33-167bzc cy7c1482v33-167bzc bb165c 165 fbga(15 x 17x1.4 mm) cy7c1486v33-167bgxc bb209a lead-free 209-ball bga (14 22 1.76 mm) cy7c1480v33-167bzxc cy7c1482v33-167bzxc bb165c lead-free 165 fbga(15 x 17x1.4 mm) shaded areas contain advance information. please contact your local sales representative for availability of these parts. lead-free bg packages (ordering code: bgx) will be available in 2005. notes: 27. device must be deselected when entering zz mode. see cycle desc riptions table for all possible signal conditions to deselect the device. 28. dqs are in high-z when exiting zz sleep mode
cy7c1480v33 cy7c1482v33 cy7c1486v33 preliminary document #: 38-05283 rev. *c page 27 of 30 package diagrams dimensions are in millimeters. 0.300.08 0.65 20.000.10 22.000.20 1.400.05 121 1.60 max. 0.05 min. 0.600.15 0 min. 0.25 0-7 (8x) stand-off r 0.08 min. typ. 0.20 max. 0.15 max. 0.20 max. r 0.08 min. 0.20 max. 14.000.10 16.000.20 0.10 see detail a detail a 1 100 30 31 50 51 80 81 gauge plane 1.00 ref. 0.20 min. seating plane 100-pin thin plastic quad flatpack (14 x 20 x 1.4 mm) a101 51-85050-*a
cy7c1480v33 cy7c1482v33 cy7c1486v33 preliminary document #: 38-05283 rev. *c page 28 of 30 package diagrams (continued) 209-ball fbga (14 x 22 x 1.76 mm) bb209a 51-85167-**
cy7c1480v33 cy7c1482v33 cy7c1486v33 preliminary document #: 38-05283 rev. *c page 29 of 30 ? cypress semiconductor corporation, 2004. the information contained herein is subject to change without notice. cypress semic onductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or ot her rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agr eement with cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to re sult in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manu facturer assumes all risk of such use and in doing so indemni fies cypress against all charges. i486 is a trademark, and intel and pentium are registered tr ademarks of intel corporation. powerpc is a trademark of ibm corporation. all product and company names mentioned in th is document are the trademarks of their respective holders. package diagrams (continued) a 1 pin 1 corner 17.000.10 15.000.10 7.00 1.00 ?0.450.05(165x) ?0.25 m c a b ?0.05 m c b a 0.15(4x) 0.35 1.40 max. seating plane 0.530.05 0.25 c 0.15 c pin 1 corner top view bottom view 2 3 4 5 6 7 8 9 10 10.00 14.00 b c d e f g h j k l m n 11 11 10 9 8 67 5 4 3 2 1 p r p r k m n l j h g f e d c b a c 1.00 5.00 0.36 +0.05 -0.10 165-ball fbga (15 x 17 x 1.40 mm) bb165c 51-85165-*a
cy7c1480v33 cy7c1482v33 cy7c1486v33 preliminary document #: 38-05283 rev. *c page 30 of 30 document history page document title: cy7c1480v33/cy7c1482v33/cy7c1486v3372-mb it (2m x 36/4m x 18/1m x 72) pipelined sync sram document number: 38-05283 rev. ecn no. issue date orig. of change description of change ** 114670 08/06/02 pks new data sheet *a 118281 01/21/03 hgk changed t co from 2.4 to 2.6 ns for 250 mhz updated features on page 1 for package offering removed 30-mhz offering updated ordering information changed advanced information to preliminary *b 233368 see ecn njy changed timing diagrams changed logic block diagrams modified functional description modified ?functional overview? section added boundary scan order for all packages included thermal numbers and capacitance values for all packages included idd and isb values removed 250-mhz speed grade offering and included 225-mhz speed bin changed package outline for 165fbga package and 209-ball bga package removed 119-bga package offering *c 299452 see ecn syt removed 225-mhz offering and included 250-mhz speed bin changed t cyc from 4.4 ns to 4.0 ns for 250-mhz speed bin changed ja from 16.8 to 24.63 c/w and jc from 3.3 to 2.28 c/w for 100 tqfp package on page # 20 added lead-free information for 100-pin tqfp, 165 fbga and 209 bga packages. added comment of ?lead-free bg packa ges availability? below the ordering information

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